1. Field of the Invention
The present invention relates to high density semiconductor devices and to methods for forming and isolating active regions and components of a high density semiconductor device.
2. Description of Related Art
Semiconductor devices typically include multiple individual components formed on or within a substrate. Such devices often comprise high density and low density sections. "High density" refers generally to an area in which elements tend to be repetitious, densely packed with consistent, but small, spacing. "Low density" refers to areas containing differing types of (e.g., non-repetitious) circuitry with greater spacing between elements. For example, referring to FIGS. 1, 2, and 2A, a memory device, such as a flash electrically erasable programmable read only memory (EEPROM) 50 commonly comprises one or more high density core regions 130 and a low density peripheral portion 150 on a single substrate 100. High density core 130 typically comprises at least one M.times.N array 104 of individually addressable, substantially identical memory cells (FIG. 2). Low density peripheral portion 150 typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells. The selective addressing circuitry typically includes one or more x-decoders and y-decoders, cooperating with the I/O circuitry for connecting the source, gate, and drain of selected addressed cells to predetermined voltages or impedances to effect designated operations on the cell, e.g., programming, reading and erasing, and deriving necessary voltages to effect such operations. Generally, circuitry in peripheral portion 150 is more varied and irregular than circuitry in core 130, and thus less subject to high density placement or formation, and, additionally, tends to handle higher voltage levels, increasing the inter-element isolation requirements of the device.
Referring now to FIGS. 2 and 2A, each cell 190 in core 130 typically comprises: source 210, drain 220, and channel 250 semiconductor regions formed in a substrate 100; and a stacked gate (word line) structure 200. Gate structure 200 suitably comprises: a thin gate dielectric layer 260 (commonly referred to as the "tunnel oxide") formed on the surface of substrate 100 overlying channel 250; a floating gate 230 overlying tunnel oxide 260; an interpoly dielectric 270 overlying floating gate 230; and a control gate 240 overlying interpoly dielectric layer 270. The control gates 240 of the respective cells 190 in a row are formed integral to a common word line (WL) associated with the row. In the completed array, the source 210 of each cell in a column (excepting end cells) is formed in a common region with one of the adjacent cells, e.g., the preceding cell in the column. Likewise, the drain of the cell is formed in a common region with the drain 220 of the other adjacent cell, e.g., next succeeding cell in the column. Additionally, the sources of each cell 190 in a row (and hence pairs of rows) are formed as a common region, facilitating formation of a common source line CS (FIG. 2A). The drain of each cell in a row of cells is connected by a conductive bit line (BL) (FIG. 2A).
Channel 250 selectively conducts current between source 210 and drain 220 in accordance with the electric field developed in channel 250 by gates 230, 240. By appropriately charging (programming) and discharging (erasing) floating gate 230, the threshold voltage V.sub.T of cell 190 (i.e., the voltage V.sub.G that must be applied to control gate 240 to cause conduction between source and drain) may be selectively varied to program cell 190.
When a cell is programmed, electrons are injected through tunnel oxide 260 to floating gate 230. The resulting negative potential on floating gate 230 generally raises the threshold voltage V.sub.T of the cell. To read the cell, a predetermined voltage V.sub.G that is greater than the threshold voltage of an unprogrammed cell, but less than the increased threshold voltage of a programmed cell, is applied to control gate 240. If the cell conducts, it is deemed unprogrammed (a first logic state, e.g. zero), and if it does not conduct it is deemed programmed (a second logic state, e.g. one).
Referring to FIG. 2A, typically, in forming an array 104 of memory cells 190 such as used in a conventional EEPROM 50, a pattern of field oxide regions 300 is initially formed within the core region, as will be discussed. Stacked gate-word line structures 200 (one corresponding to each row) are then formed, followed by further etching and dopant implantation in exposed regions of substrate 100 (in predetermined disposition to stacked gate structures 200) to form the source and drain regions of the respective cells 190.
Electrical isolation between the respective devices of memory device 50 is typically effected using respective field oxide regions. For example, field oxide regions are used to provide isolation between array 104 in core region 130 from the devices of peripheral region 150, as well as between the various columns of cells 190 within core region 130. Field oxide regions are conventionally formed using a mask and selective growth process as will be discussed. In general, within core 130, the selective growth process results in alternating parallel strips of field oxide 300 and exposed regions corresponding to the columns of cells 190 in the array.
Referring to FIG. 3, field oxide regions 300 are conventionally formed by, for example: growing a layer of thermal oxide ("barrier oxide" or "pad oxide") 110, over the surface of substrate 100. A masking layer 120, frequently composed of nitride, is deposited on barrier oxide 110, and patterned to cover those regions 370 of substrate 100 in which devices are to be formed (herein referred to as active regions 370).
Referring to FIG. 4, after patterning masking layer 120, a field oxide 300 is grown in the exposed areas of the barrier oxide 110, by for example, local oxidation of silicon (LOCOS). Field oxide 300 provides electrical isolation of the various active regions 370. After growing field oxide 300, masking layer 120 and barrier oxide 110 are stripped to expose the underlying substrate 100. During the field oxide growth phase, although the nitride of masking layer 120 prevents direct exposure of the underlying barrier oxide 110, oxygen diffuses under the edges of the nitride and partially oxidizes the underlying barrier oxide 110. Diffusion of oxygen under the nitride causes lateral encroachments of field oxide 300, commonly referred to as "birds' beaks" 350.
Birds' beaks 350 present a recurring problem in the manufacturing process by reducing the area of active regions 370, for example by length L.sub.BB, on each side of active region 370. For applications requiring very small active regions, birds' beaks 350 complicate the manufacturing process and, indeed, can present a limiting factor to density. Birds' beaks 350 may also grow large enough to cause "punch through," in which adjacent birds' beaks 350 become large enough to meet under the nitride, effectively destroying active region 370. In addition, the different oxidation rates that form birds' beaks 350 induce stress-related problems, such as crystal dislocation defects in the substrate, that degrade performance. Furthermore, in high packing density applications, field oxide 300 may not grow fully in very narrow spaces between active regions 370, resulting in unreliable isolation of the active regions 370.
Several techniques have been proposed to eliminate birds' beaks and their drawbacks, such as trench isolation, sealed interface LOCOS (SILO), and sidewall mask isolation (SWAMI) techniques. In trench isolation processes, a trench is etched in the substrate surrounding an active region and the trench filled with an electrically insulating material. The insulating material, however, often damages the walls of the trench, which allows a leakage current to flow between the source and drain under the gate. Trenches also tend to produce stress-induced crystal defects, particularly at sharp comers created during the formation of the trench.
Sealed interface LOCOS (SILO) techniques eliminate the pad or barrier oxide; the entire surface of the substrate is thermally nitridized. A second layer of nitride is deposited on the thermal nitride, both the first and second nitride layers are patterned and etched, and the exposed portion of the substrate is oxidized to form field oxide regions. The thermal (or first) nitride layer is used to prevent lateral oxidation, i.e., formation of birds' beaks. Various aspects of SILO technology are discussed in "Physical and Electrical Characterization of a SILO Isolation Structure," Deroux-Dauphin, et al., IEEE Transactions on Electron Devices, Vol. ED-32, No. 11, p. 2392, November, 1985.
The SILO process, however, may cause stress-induced defects due to, among other things, the brittleness of the thermal nitride and the different thermal expansion characteristics of the thermal nitride and the silicon substrate. Stress-induced defects include dislocation defects and stacking faults, which decade performance.
SWAMI combines trench isolation and LOCOS techniques. A trench is initially etched in the silicon substrate and then covers the surface of the substrate and the sidewalls of the trench with a nitride layer. The nitride layer is removed from the bottom of the trench to thermally oxidize the underlying substrate exposed at the bottom of the trench, which fills the trench with oxide. Like other trench isolation methods, SWAMI frequently causes stress-induced defects due to oxidation of the substrate in an area confined by the nitride layer. Various aspects of SWAMI technology are discussed in "Electrical Properties for MOS LSI's Fabricated Using Stacked Oxide SWAMI Technology," Sawada, et al., IEEE Transactions on Electron Devices, Col. ED-32, No. 11, p. 2243, November, 1985.
In addition to the problems and limitations created by birds' beaks 350, reductions in the size of cell 190 are further limited by minimum control gate-floating gate coupling requirements. To effect a charge on floating gate 230, the voltage on control gate 240 is capacitively coupled to floating gate 230, which permits control gate 240 to control the voltage on floating gate 230. Inadequate capacitive coupling between control gate 240 and floating gate 230, however, inhibits proper operation of cell 190.
The degree of capacitive coupling is significantly affected by the overlapping surface area of gates 230 and 240. Referring again to FIG. 2, control gate 240 and floating gate 230 conventionally comprises parallel planes of conductive material (separated by interpoly dielectric 270). Increased overlapping surface area of gates 230, 240 contributes to greater capacitive coupling. If the area of either gate 230 and 240 is too small, however, the effectiveness of the coupling degrades and adversely affects the threshold voltage. Consequently, each gate 230, 240 must provide sufficient area to effectively couple control gate 240 to floating gate 230. This factor operates as an effective minimum, below which cell 190 may not operate properly. As a result, efforts to reduce the size of cells 190 in core area 130 are limited by the minimum size of gates 230 and 240.
In sum, the problems associated with birds' beaks decade the reliability of the design and manufacturing process. Although techniques have been devised to alleviate these difficulties, these techniques provide limited success and often induce other defects. As a result, the problems presented by birds' beaks remain unsolved. In addition, the requisite surface area of each control gate 240 and floating gate 230 also tend to limit reductions in the size of cell 190, presenting device packing density limitations.